VSRV1 - 32-bit Linux-capable RISC-V Core

VSRV1 is a simple 32-bit RISC-V CPU that is able to run applications and standard protocol stacks (for example ethernet) under the Linux operating system.

The VSRV1 core is based on the scalar version of the ultraembedded core available at https://github.com/ultraembedded. The core is fully rewritten in VHDL. It can be used in both ASIC and FPGA implementations. It has very few compilation options; the main ones are related to cache sizes, so it's easy to get started with.

License

VSRV1 is licensed under Solderpad Hardware License v2.

Features

VSRV1 is a 32-bit RISCV ISA CPU core which supports integer (I), multiplication and division (M), CSR instructions (Z), and supervisory (S) extensions (RV32IMS zicsr zifencei). It has also a rudimentary MMU unit. The "summary of the features" drawing gives a graphical overview of the main features.

VSRV1 has two internal memory configurations available:

• core with tightly coupled memory (default with 64KiW (256KiB) dual-port RAM)
• core with instruction and data cache (configurable cache sizes and ways)

The external memory interface uses the AXI4 bus. We have used an in-house LPDDR2 interface which is not included in the deliveries. FPGA users can use any LPDDR interface supported by the FPGA.

The VSRV1 example FPGA setup uses UART, SPI and timer peripherals. Images/setups for Arria 10 device (10AX022C4U19E3SG) and Gidel board (Stratix II device EP2S130F1020C5) are available in the "fpga" directory of the repository.