ASICs can be roughly categorized into digital, mixed signal and analog ASICs. VLSI Solution specializes in mixed signal ones, especially the ones requiring digital signal processing (DSP) with analog and digital interfaces. We also do fully digital and almost fully analog ASICs. 

From the point of view of design effort, there are three groups:

• Firmware modifications of a standard product
• ASICs based on VLSI Solution's existing IP
• ASIC's that require new IP development

Weather the development and production of an ASIC is a sensible option for a particular system depends on many aspects.

• volume per year
• life time
• cost
• IP protection
• level of integration
• size of the device
• programmability

Generally, it is better to look the whole existing system for ASIC optimization with us rather than trying to replace a single component.

An ASIC design project consists of five main stages: specification, design, prototype manufacturing with possibly several rounds, evaluation and transfer to production.

Specification

After the initial feasibility analysis, the first step of an ASIC project is always the writing of a specification. At this stage the overall system architecture is analyzed and optimized, this usually involves deciding which functions should be implemented with the ASIC and determining their specifications.

For any system that has a processor, whether it's DSP or general purpose processor, a key design factor is the partitioning between tasks done with software and hardware. This may require actually writing large amounts of software to verify the sensibility of the choices. The software can be tested with a virtual prototype, with ASIC or with a prototype system build on a PCB with off-the-self components. 

If the system design already exists, the system design can be fairly straightforward, but if the whole system is new or requires many alterations, many iterations may be needed. Sometimes even a prototype ASIC is required before the system design can be finalized. 

For the hardware part, the final document of the specification stage is usually a datasheet of the ASIC.

At the specification stage also a suitable implementation technology is chosen. This can be 0.18um CMOS or some special technology for mainly analog designs or design requiring no more than one processor core. For mixed signal designs with more logic, but still requiring high performance analog, 0.13um could be a good choice. For mostly digital designs not requiring high performance analog, any technology down to 22nm can be used. Newest FinFET projects (below 7nm) require bigger teams than we can offer.

Design and prototyping 

After the specification is finalized, the actual ASIC design can be started. This will require at least half a year, but typically significantly longer. The minimum time requires that all the IP is ready for the selected technology and the top level design is straightforward. In the minimum effort case the top level integration and verification is simple and most of the time is used for the back end, i.e. generating the layout. 

For digital part of the design, an important verification round is prototyping with FPGA.

Prototypes are usually manufactured in an MPW (multi project wafer) run. This is a relatively low cost way of doing a prototype, but has schedule limitations, which may delay the project. 

Software

In highly analog or mixed-signal ASICS, the digital signal processing software usually comes from us. Occasionally customer may have IP (such as DSP routine) and development is done in co-operation with the customer. User interface is typically done by the customer. We help just with the library functions for the interface.

In highly digital designs the software is usually the biggest cost center of the project. The prototyping phase by using FPGA and PCB for the interfaces as well as simulations will take considerable effort before test chip can be implemented.

Package Selection

Package selection is an important part of the ASIC project. Package selection affecting parameters are the target cost, maximum size and environmental reliability requirements. Even though we can design and qualify custom packages and support multi-die packaging, the standard leadframe or substrate based packages are usually the best selection for projects which require less than couple hundred IO pins.

Evaluation

The evaluation is always planned during the design phase. A key part of the evaluation is the prototyping board (PCB), which is designed parallel with the package selection and backend design.

Transfer to manufacturing

The test program development is crucial part when prototype is transferred to production. We use our own IC testers and just adaptation board (Loadboard) and test sockets will be needed per project.

The purpose of the test program is to measure every single atomic component (transistor, resistor, capacitor and inductor) of the chip. To achieve test coverage of over 96% testability must be considered already in design phase of the project.

The most important tests of "transfer to manufacturing" phase are electrical-temperature characterization and accelerated biased life tests. The electrical-temperature characterization test uses the IC tester to loop all operating voltages from minimum to maximum by using maximum amount of electrical test of the chip, and repeat this loop at least in three temperatures (such as -40, +25, +85 degC). In the accelerated biased life test we will be aging set of devices long time (1000-5000 hours) in high temperature (+125degC) with maximal electrical activity and maximum voltages.

The duration of this phase is three months minimum and typically about six months.

The characterization is done first with the prototypes. When tests pass the design is considered robust enough for the single product mask order. Production masks are expensive and the work described above tries to minimize the risk to order masks for a product which has design or process issues causing low yield and high cost in volume production.

As a final step, three first production lots are also characterized and they need to pass the qualification tests again. Additionally, the statistical numbers (such as yield, cp, cpk) are all compared with the in-house standards and expectations. When needed, individual masks can be modified for better yield or performance.

All costs are highly depending on the nature of the project. It is better to contact us and discuss the cost related things always under NDA.

The costs can be divided roughly to the following sections

• Specification and prototyping with PCB and FPGA
• IP cost (in case external IP is needed)
• Chip design and backend work
• IC prototyping cost (MPW dies and packaging)
• Redesign and changes
• Transfer to production

As first step we encourage to send email to sales@vlsi.fi and describe your project on the level that does not require NDA.

We will response within two working days and ask clarifications and/or suggest Teams/Meet/Zoom meeting.

When both parties understand enough about the project and want to co-operate it is time to sign NDAs and start exchange block diagrams, data flows etc. specifications related to the project.

When working with us, please note that we want that minimum amount of information is confidential. Otherwise every project we do limits our capabilities in the future projects.